The present invention relates generally to integrated circuits, and, more particularly, to a successive approximation register analog-to-digital converter.
Data converters including analog-to-digital converters (ADC) are commonly used in electronic devices like wireless communication systems, and audio and video systems. The ADCs can be of different types such as flash ADCs, pipelined ADCs, successive approximation register (SAR) ADCs, etc. An n-bit SAR ADC uses a binary search algorithm to convert a continuous analog input signal to an n-bit digital signal. For example, a 10-bit SAR ADC converts an analog input signal into a corresponding 10-bit digital signal. The SAR ADC performs repetitive comparisons of the analog input signal with a sequence of known binary-weighted values to estimate the binary value of the digital signal.
A SAR ADC includes a DAC, a differential comparator, and a SAR register. The SAR register is connected between the DAC and the comparator in a feedback loop. The DAC includes a plurality of binary-weighted circuit elements such as capacitors and resistors. In the above example, the 10-bit SAR ADC has a 10-bit DAC that has ten binary-weighted capacitors for generating the 10-bit digital signal. Each binary-weighted capacitor corresponds to a binary digit of the 10-bit digital signal. The SAR ADC performs the analog-to-digital conversion over two phases, a sample phase and a compare phase. During the sample phase, the SAR ADC samples the analog input signal and generates a sampled analog input signal. During the compare phase, the binary-weighted circuit elements successively approximate the sampled analog input signal by comparing the sampled analog input signal with a series of comparison voltages that correspond to a series of binary values. A first comparison voltage corresponds to a binary value with the most significant bit (MSB) as binary one and the subsequent binary digits as zeros. If the differential comparator determines that the sampled analog input signal is greater than the first comparison voltage in a first comparison cycle (in the compare phase), then an MSB of the digital signal corresponding to the sampled analog input signal is set as binary one and stored in the SAR register; and if the comparator determines that the sampled analog input signal is less than the first comparison voltage, then the MSB is set as zero and stored in the SAR register. A second comparison voltage corresponds to a binary value with the MSB set to binary one or zero based on the first comparison cycle, the binary digit subsequent to the MSB (referred to as a next MSB) set as binary one and the subsequent binary digits set as binary zero. Hence, in each cycle of comparison, a successive comparison voltage of the series of comparison voltages is either half of the preceding comparison voltage or a sum of or difference between half of the preceding comparison voltage and half of a successive voltage range. This process is repeated to determine each binary digit of the digital signal. At the end of the compare phase, the binary values stored in the SAR register represent the digital signal that corresponds to the analog input signal.
SAR ADCs are susceptible to manufacturing defects, such as incorrect capacitance and resistance values of the binary-weighted circuit elements, a defective differential comparator, and so forth, which can lead to generation of an erroneous digital signal. The accuracy of the SAR ADC largely depends on error-free operation of the differential comparator. In order to operate with analog input signals having high voltage levels, the differential comparator includes metal-oxide semiconductor field-effect-transistors (MOSFETs) having stacked gate-oxide layers. The stacking of the gate-oxide layers is done at a nitrous oxide (N2O) annealing stage during fabrication of the differential comparator. However, during the N2O annealing stage some traps or gaps may be formed in the gate-oxide layers due to surrounding impurities. When such MOSFETs are subjected to high gate-to-source voltages (VGS) for time intervals in units of microseconds, a transient shift in threshold voltages of the MOSFETs occurs as electrons get trapped in the gaps formed in the gate-oxide layers of the MOSFETs due to development of a high electric field in the gate-oxide layers. Over longer time periods, the high electric field effect diminishes and the transient shift in the threshold voltages disappears, thereby restoring the actual threshold voltages. However, a dynamic offset voltage exists in the differential comparator due to this transient shift in the threshold voltages. The dynamic offset voltage may typically occur during the successive approximation steps of the SAR ADC and cause errors, such as differential-nonlinearity (DNL) spikes and missing binary values.
Therefore, it would be advantageous to have a SAR ADC that is not susceptible to errors caused by DNL spikes and missing binary values.